Embedded ROM device using substrate leakage

ABSTRACT

A ROM embedded DRAM provides ROM cells that can be programmed to a single state. The ROM cells include capacitors having a storage node. The storage node is processed to have a substantially high substrate leakage. The ROM cells, therefore, are hard programmed to a logic zero state. Bias techniques can be used to read un-programmed ROM cells accurately. As described, sense amplifier circuitry can be offset in one embodiment to default to the un-programmed state. In another embodiment, bias circuitry is coupled to bit lines to favor the un-programmed state. A differential pre-charge operation can also be used in another embodiment.

RELATED APPLICATIONS

This is a continuation application of U.S. patent application Ser. No.10/194,549, titled “EMBEDDED ROM DEVICE USING SUBSTRATE LEAKAGE,” filedJul. 11, 2002 now U.S. Pat. No. 6,781,867 (allowed), which applicationis assigned to the assignee of the present invention and the entirecontents of which are incorporated herein by reference.

TECHNICAL FIELD OF THE INVENTION

The present invention relates generally to memory devices and inparticular the present invention relates to read only memory (ROM)embedded in a dynamic random access memory (DRAM).

BACKGROUND OF THE INVENTION

Semiconductor memory systems are comprised of two basic elements: memorystorage areas and memory control areas. DRAM, for example, includes amemory cell array, which stores information, and peripheral circuitry,which controls the operation of the memory cell array.

DRAM arrays are manufactured by replicating millions of identicalcircuit elements, known as DRAM cells, on a single semiconductor wafer.A DRAM cell is an addressable location that can store one bit (binarydigit) of data. In its most common form, a DRAM cell consists of twocircuit components: a storage capacitor and an access field effecttransistor. The capacitor holds the value of each cell, namely a “1” ora “0,” as a charge on the capacitor. Because the charge on a capacitorgradually leaks away, DRAM capacitors must be refreshed on a regularbasis. A memory device incorporating a DRAM memory includes logic torefresh (recharge) the capacitors of the cells periodically or theinformation will be lost. Reading the stored data in a cell and thenwriting the data back into the cell at a predefined voltage levelrefreshes a cell. The required refreshing operation is what makes DRAMmemory dynamic rather than static.

The transistor of a DRAM cell is a switch to let control circuitry forthe RAM either read the capacitor value or to change its state. Thetransistor is controlled by a row line coupled to its gate connection.In a read operation, the transistor is activated and sense amplifierscoupled to bit lines (column) determine the level of charge stored inthe memory cell capacitor, and reads the charge out as either a “1” or a“0” depending upon the level of charge in the capacitor. In a writeoperation, the sense amplifier is over-powered and the memory cellcapacitor is charged to an appropriate level.

Frequently, as in the case of microprocessors, microcontrollers, andother application specific integrated circuitry (ASICs), it is desiredto incorporate read only memory (ROM) together with or in addition toRAM on a single semiconductor wafer. This typically requires theformation of separate additional peripheral circuitry and interconnectsfor the ROM. The ROM cells and additional circuitry require additionalsemiconductor wafer space and fabrication process steps that increasethe overall costs of device fabrication.

A read only memory (ROM) consists of an array of semiconductor devices(diodes, bipolar or field-effect transistors), which interconnect tostore an array of binary data (ones or zeros). A ROM basically consistsof a memory array of programmed data and a decoder to select the datalocated at a desired address in the memory array.

Three basic types of ROMs are mask-programmable ROMs, erasableprogrammable ROMs (EPROMs) and field-programmable ROMs (PROMs). The dataarray is permanently stored in a mask-programmable ROM, at the time ofmanufacture, by selectively including or omitting the switching elementsat the row-column intersections in the memory array. This requires aspecial mask used during fabrication of the integrated circuit, which isexpensive and feasible only when a large quantity of the same data arrayis required. EPROMs use a special charge-storage mechanism to enable ordisable the switching elements in the memory array. In this case,appropriate voltage pulses to store electrical charges at the memoryarray locations are provided. The data stored in this manner isgenerally permanent until it is erased using ultraviolet light allowingit to once again be programmed. PROMs are typically manufactured withall switching elements present in the array, with the connection at eachrow-column intersection being made by means of either a fuse element oran anti-fuse element. In order to store data in the PROM, these elements(either the fuse or the anti-fuse, whichever are used in the design) areselectively programmed using appropriate voltage pulses supplied by aPROM programmer. Once the elements are programmed, the data ispermanently stored in the memory array.

Programmable links have been used extensively in programmable read onlymemory (PROM) devices. Probably the most common form of programmablelink is a fusible link. When a user receives a PROM device from amanufacturer, it usually consists of an X-Y matrix or lattice ofconductors or semiconductors. At each cross-over point of the lattice aconducting link, call a fusible link, connects a transistor or otherelectronic node to this lattice network. The PROM is programmed byblowing the fusible links to selected nodes and creating an opencircuit. The combination of blown and unblown links represents a digitalbit pattern of ones and zeros signifying data that the user wishes tostore in the PROM. By providing an address the data stored on a node maybe retrieved during a read operation.

In recent years, a second type of programmable link, call an anti-fuselink, has been developed for use in integrated circuit applications.Instead of the programming mechanism causing an open circuit as in thecase with fusible links, the programming mechanism in an anti-fusecircuit creates a short circuit or relatively low resistance link. Thusthe anti-fuse link presents an open circuit prior to programming and alow resistance connection after programming. Anti-fuse links consist oftwo electrodes comprised of conductive and/or semiconductive materialsand having some kind of a dielectric or insulating material betweenthem. During programming, the dielectric in between the conductivematerials is broken down by predetermined applied voltages, therebyelectrically connecting the conducting and/or semiconducting materialstogether.

Like RAM cells, ROM cells need to store either a data 1 or a data 0.Processing factors, however, may limit the ROM cell to only one programstate. For the reasons stated above, and for other reasons stated belowwhich will become apparent to those skilled in the art upon reading andunderstanding the present specification, there is a need in the art fora ROM-embedded-DRAM which can be fabricated with single state ROM cells.

SUMMARY OF THE INVENTION

The above-mentioned problems with ROM-embedded-DRAM and other problemsare addressed by the present invention and will be understood by readingand studying the following specification.

In one embodiment, a memory device comprises an array of dynamic memorycells and an array of read only memory (ROM) cells. Each dynamic memorycell comprises a storage capacitor having a first plate to store anelectrical charge. Each ROM cell comprises a storage capacitor having afirst plate coupled to discharge an electrical charge such that thedynamic memory cells retain a charge substantially longer than the ROMcells.

In another embodiment, an integrated circuit ROM embedded DRAM comprisesan array of dynamic memory cells and an array of read only memory (ROM)cells. Each dynamic memory cell comprises a storage capacitor having astorage plate coupled to first active area regions of a substrate. Thefirst active area regions and the substrate have opposite electricaldoping such that a first substrate leakage current from the first activearea regions to the substrate is small to retain a charge on the storageplate. Each ROM cell comprises a storage capacitor having a storageplate coupled to second active area regions of a substrate. The secondactive area regions are doped such that a second substrate leakagecurrent from the second active area regions to the substrate is greaterthan the first substrate leakage current to discharge the second storageplaces substantially faster than the first storage plates.

A method of programming an integrated circuit read only memory (ROM)cell is provided and comprises implanting N+ material into a P-substrateto form an active area, implanting a P-type material into the activearea to enhance a leakage current from the active area to the substrate,and forming a cell capacitor having a storage plate electrically coupledto the active area.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a simplified block diagram of a ROM embedded DRAM of anembodiment of the present invention;

FIG. 2 is a cross-section of a fabrication of a ROM-embedded-DRAM of anembodiment of the present invention;

FIG. 3 is another cross-section of the ROM-embedded-DRAM of FIG. 2;

FIG. 4 illustrates a pair of complementary digit lines of the memory ofFIG. 1;

FIG. 5 illustrates a pair of complementary digit lines and referencecells of an embodiment of the memory of FIG. 1;

FIG. 6 is a simplified timing diagram of operation of an embodiment ofthe memory of FIG. 5;

FIG. 7 is another simplified timing diagram of operation of anembodiment of the memory of FIG. 5; and

FIG. 8 is a timing diagram of a pre-charge and refresh operation of anembodiment of the memory of FIG. 1.

DETAILED DESCRIPTION OF THE INVENTION

In the following detailed description of the invention, reference ismade to the accompanying drawings that form a part hereof, and in whichis shown, by way of illustration, specific embodiments in which theinvention may be practiced. In the drawings, like numerals describesubstantially similar components throughout the several views. Theseembodiments are described in sufficient detail to enable those skilledin the art to practice the invention. Other embodiments may be utilizedand structural, logical, and electrical changes may be made withoutdeparting from the scope of the present invention. The terms wafer andsubstrate used in the following description include any structure havingan exposed surface with which to form the integrated circuit (IC)structure of the invention. The term substrate is understood to includesemiconductor wafers. The term substrate is also used to refer tosemiconductor structures during processing, and may include other layersthat have been fabricated thereupon. Both wafer and substrate includedoped and undoped semiconductors, epitaxial semiconductor layerssupported by a base semiconductor or insulator, as well as othersemiconductor structures well known to one skilled in the art. The termconductor is understood to include semiconductors, and the terminsulator is defined to include any material that is less electricallyconductive than the materials referred to as conductors. The followingdetailed description is, therefore, not to be taken in a limiting sense,and the scope of the present invention is defined only by the appendedclaims, along with the full scope of equivalents to which such claimsare entitled.

Referring to FIG. 1, a simplified block diagram of a ROM embedded DRAM300 of the present invention is described. The memory device can becoupled to a processor 310 for bi-directional data communication. Thememory includes an array of memory cells 312. The array includes adynamic (DRAM) portion 320 and a read only (ROM) portion 322. The ROMarray is “embedded” in the dynamic memory and may include some dynamiccells. Control circuitry 324 is provided to manage data storage andretrieval from the array in response to control signals 340 from theprocessor. Address circuitry 326, X-decoder 328 and Y-decoder 330analyze address signals 342 and storage access locations of the array.Sense circuitry 332 is used to read data from the array and coupleoutput data to I/O circuitry 334. The I/O circuitry operates in abi-directional manner to receive data from processor 310 and pass thisdata to array 312. It is noted that the sense circuitry may not be usedin some embodiments to store the input data.

Dynamic memories are well known, and those skilled in the art willappreciate the that the above-described ROM embedded DRAM has beensimplified to provide a basic understanding of DRAM technology and isnot intended to describe all of the features of a DRAM. The presentinvention uses the basic architecture and fabrication techniques of aDRAM and provides an embedded ROM array for non-volatile storage ofdata. This data can be used to store boot-type data for a system, anon-volatile look-up table, or other data that does not require adedicated ROM memory device. Embedding ROM storage in a DRAM is mosteconomically beneficial if the DRAM is not substantially altered duringfabrication or operation. That is, small fabrication changes allow theembedded memory to be fabricated using known techniques. Further, it isdesired to maintain operation of the memory in a manner that isexternally transparent. As such, an external processor, or system, doesnot need special protocol to interface with the embedded memory.

One technique for physically programming ROM embedded cells is describedin U.S. Pat. No. 6,134,137 issued Oct. 17, 2000 entitled“ROM-Embedded-DRAM”, incorporated herein by reference. U.S. Pat. No.6,134,137 teaches that slight modifications in fabrication masks allowDRAM cells to be hard programmed to Vcc or Vss by shorting the cell towordlines. The memory reads the ROM cells in a manner that is identicalto reading the DRAM cells. As described below, the present inventionprovides an improved ROM embedded DRAM.

As explained above, conventional ROM devices program two data states,logic 1 and 0. When the memory cells are read, therefore, both datastates are readily available. In contrast, the present inventionprovides a combination ROM and DRAM memory device. The ROM memory cellsare programmed to one data state, while the DRAM memory cells areprogrammed and refreshed to a complimentary data state. This can beaccomplished by shorting selected cells to one voltage and programmingall cells to a complementary state. The cells that are shorted remainprogrammed in a non-volatile manner, while the remaining cells areprogrammed to the complimentary state in a volatile manner. For example,ROM memory cells can be programmed to a ground potential state (logic 0)by discharging the DRAM memory cell to the substrate, as explainedbelow. The ROM cells are pre-programmed prior to operation to a logic 1value, for example Vcc. The cells that are hard programmed to a logic 0state return to a logic 0 state, while the remaining cells aredynamically programmed to logic 1.

In an alternative embodiment, the ROM embedded DRAM can include senseamplifier circuitry that is biased to read an un-programmed DRAM cell asa logic 1 (charged). As such, a programmed ROM having a high cellleakage is read as a logic 0 and the remaining un-programmed DRAM cellsare read as a one. After describing ROM hard programming using cellleakage, bias techniques for sensing unprogrammed cells are explained.

Referring now to FIG. 2, a semiconductor wafer cross section at an earlyprocessing step is indicated generally by reference numeral 100. Thesemiconductor wafer 100 is comprised of a bulk silicon substrate 112with field isolation oxide regions 114 and active areas 116, 118, 120formed therein. Word lines 122, 124, 126, 128 have been constructed onthe wafer 100 in a conventional manner. Each wordline consists of alower gate oxide 130, a lower poly layer 132, a higher conductivitysilicide layer 134 and an insulating silicon nitride cap 136. Eachwordline has also been provided with insulating spacers 138, which arealso composed of silicon nitride.

Two FETs are depicted in FIG. 2. One FET is comprised of two activeareas (source/drain) 116, 118 separated to form a channel region and onewordline (gate) 124. The second FET is comprised of two active areas(source/drain) 118, 120 and a second wordline (gate) 126. The activearea 118 common to both FETs is the active area over which a bit linecontact will be formed. One bit line contact is shared by two DRAM cellsto conserve space.

Active areas 116, 118 and 120 are formed by an implant operation. In oneembodiment, the substrate is a P-type substrate, or well, and the activeareas are doped as N+ regions. In standard DRAM fabrication, the cellactive areas are created to reduce leakage to the substrate. That is,the active areas form a PN diode junction with the substrate. This diodejunction is typically controlled to minimize leakage from the DRAM celland extend data retention times. In contrast, the present inventionweakens the diode junction to hard program a ROM cell. In oneembodiment, active area 116 is counter doped with a P-type material. Forexample, a selective boron implant can be performed on the junctionregion to provide a weak N-type region. It will be appreciated by thoseskilled in the art with the benefit of the present invention, that othertechniques can be used to increase the leakage of the ROM cell. In oneembodiment, the ROM cell has a substrate leakage current that is anorder of magnitude greater than the DRAM cell substrate leakage current.

As explained above, one embodiment of reading complimentary memory cellstates includes programming all memory cells to a logic 1 charged state.After the ROM and DRAM cells are pre-programmed to a charged state, thehard programmed ROM cells discharge through the weak diode region. Itwill be appreciated that a fast discharge can increase programming andrefresh currents, while a slower discharge time requires more time,following pre-charge, before reading the memory cells. Likewise, a fastdischarge may have a slight coupling influence on the substrate voltage.

Referring to FIG. 3, the processed ROM embedded DRAM cross-section isfurther explained. A thin layer 140 of nitride or TEOS (tetraethylorthosilicate) is provided adjacent to spacers 138 and above nitride cap136. A layer of insulating material 142 is deposited over layer 140 andcap 136. The insulating material preferably consists ofborophosphosilicate glass (BPSG). Conductive plugs 146 are formed incontact with the active areas 116, 118, 120. An example of the materialused to form conductive plug layer 146 is in situ arsenic or phosphorousdoped poly. An additional layer 148 of BPSG is deposited on insulator142.

Conductive storage node 152 (lower electrode) of the capacitor isprovided. Node 152 may be formed of hemispherical grained poly (HSG) toincrease capacitance. If HSG poly is used, the layer 152 may be formedby first depositing a layer of in situ doped polysilicon followed by adeposition of undoped HSG. Subsequent heating inherent in waferprocessing effectively conductively dopes the overlying HSG layer.Alternatively, node 152 may be provided by in situ arsenic doping of anentire HSG layer. Node 152 is in electrical contact with plugs 146 overthe non-bit line active areas 116, 120. A capacitor dielectric layer 154is provided over a second BPSG layer 148 and over the conductive node152. The dielectric layer 154 may comprise a Ta₂O₅ oroxide-nitride-oxide (ONO) dielectric, although other materials are ofcourse possible.

A second conductive node 156 is provided over the dielectric layer 154.The second conductive node 156 is preferably composed of poly. Inaddition to serving as a second plate of the capacitor, the secondconductive node 156 also forms the interconnection lines between thesecond plates of capacitors. A bit line insulating layer 158 is providedover the second conductive layer 156 and the second BPSG layer 148. Thebit line insulating layer 158 may be comprised of BPSG. A bit linecontact 160 is provided such that the bit line contact is in electricalcontact with plug 146. Thus, plug 146 over the active area 118 acts as abit line contact to ROM cell 161 and DRAM cell 162.

A ROM-embedded-DRAM has been described using a stacked capacitorfabrication technique where the active area of the ROM cell has arelatively large substrate leakage. Various other capacitor structuresand fabrication steps may be employed to fabricate capacitors to formROM cells. Any desired configuration of the ROM-embedded-DRAM accordingto the invention can be achieved given the teachings herein. Althoughthe process was depicted with reference to a stacked container capacitorprocess flow, it may be easily adapted to a process utilizing block,trench, double cylindrical, crown shaped, ring or vertical fincapacitors. Such ROM-embedded-DRAM memory cells and arrays can beconstructed in accordance with known processing techniques by one ofordinary skill in the art, given the ROM-embedded-DRAM structures andprocessing techniques taught herein.

The array may then be completed using processing techniques that arewell known in the art, including opening holes in the overlayinginsulator glass to the polysilicon periphery plugs, metalizing the holesvia tungsten plugs or aluminum force fill, and then patterning andetching conductive lines on the surface to form local interconnects.Although only preferred embodiments of the process have been disclosedherein, it will be obvious to those having ordinary skill in the artthat changes and modifications may be made to the process withoutdeparting from the scope and spirit of the invention as claimed. Forexample, the process of the invention may be performed to fabricatearrays having straight-line, as opposed to the S-shaped. Similarly,other dielectric materials such as silicon dioxide, titanium oxide,yttrium oxide, barium strontium titanate, combinations of these, andothers, may be used for dielectric 154, and other insulating materials,such as the above and various other oxides, may be substituted for theBPSG of layer 142. Additionally, materials other than HSG or CHSG (e.g.,cylindrical grain poly (CGP)) may be substituted for rugged polysiliconlayer.

FIG. 4 illustrates a pair of complementary digit lines, or bit lines202A and 202B respectively. Specifically, FIG. 4 is a schematic diagramillustrating a detailed portion of a sense amplifier circuit and relatedauxiliary connection circuitry. The schematic 200 includes anillustration of devices for digit line equilibration shown collectivelyas 206, a p-sense amplifier 210, as well as an n-sense amplifier 212.The p-sense amplifier 210 includes a pair of cross-coupled p-channeltransistors, Q1 and Q2 respectively. A first common node 218 is coupledto the pair of p-channel transistors Q1 and Q2. In one embodiment,common node 218 includes electrical coupling to an active pull-up (ACT)270 or power voltage supply node through an enable p-sense amplifier(EPSA*) transistor 219. In one embodiment, the ACT 270 couples a Vccvoltage supply to the common node 218. In another embodiment, ACT 270couples a different bias to common node 218.

The n-sense amplifier 212 includes a pair of cross-coupled n-channeltransistors, Q3 and Q4 respectively. The n-sense amplifier 212 and thep-sense amplifier 210 are further coupled to a complementary pair ofbitlines, or digitlines 202A and 202B. Memory cells, 214 ₁, . . . , 214_(N), etc., located at the intersection of digitlines 202A and 202B andwordlines 220 ₁, . . . , 220 _(M). Each n-channel transistor, Q3 and Q4,of the n-sense amplifier is independently coupled to an n-senseamplifier bus line, RNL*A and RNL*B respectively. In operation, then-sense amplifier bus lines, RNL*A and RNL*B, couple each n-channeltransistor, Q3 and Q4, to an n-sense amplifier latch signal, NLAT₁ andNLAT₂.

The coupling of the NLAT₁ and NLAT₂ to each n-channel transistor, Q3 andQ4 is controlled by a series of gate transistors shown collectively as211. In one embodiment, the gate transistors are operated by bias, 208Aand 208B. The bias signals 208A and 208B are applied in the alternative.Applying bias 208A couples NLAT₁ to RNL*A and NLAT₂ to RNL*B. Applyingbias 208B has the opposite resultant effect. In one embodiment, NLAT₁ isat a potential of Vcc/2 (or DVC2) and NLAT₂ is at a potential of Vcc/2+(or DVC2+), slightly greater than DVC2. In one embodiment, DVC2+ isapproximately 50 millivolts (mV) higher than the potential of DVC2.These potentials are placed on the respective n-sense amplifier buslines, RNL*A or RNL*B depending on which bias, 208A or 208B, isselected. Thus, NLAT is at a potential of DVC2 and NLAT₂ is at apotential of DVC2+ when bias 208A is chosen. N-sense amplifier buslines, RNL* is biased to DVC2 and RNL*B is biased to DVC2+. ACT 270meanwhile is biased to Vss or signal ground. The digitlines are bothinitially equilibrated at Vcc/2. Thus, the n-sense amplifier transistorsand p-sense amplifier transistors are off. When the memory cell isaccessed, a signal develops across the complementary digitline pair.While one digitline contains charge from the cell accessed, the otherdigitline does not and serves as a reference for the sensing operation.

In operation, the n-sense amplifier is fired by bringing, NLAT₁ andNLAT₂, toward ground. As the voltage difference between NLAT₁ and thereference digitline, and between NLAT₂ and digitline and approaches Vt,the n-channel transistor whose gate is connected to the higher voltagedigitline begins to conduct. This conduction is further assisted,however, by the fact that NLAT₁ with the DVC2 bias pulls to ground morequickly, reaching that transistor's saturation conduction region morerapidly. Thus, even if the signal difference across the complementarydigitline pair is not very clear or distinguishable, one of then-channel transistors is biased to turn on more quickly, favoring alogical “1” read. The remainder of the sensing operation occurs as knownto those skilled in the art. The conduction of the n-channel transistorcauses the low-voltage digitline to be discharged toward the NLAT*voltage. Ultimately, NLAT* reaches ground, and the digitline is broughtto ground potential. The p-sense amplifier is next fired and the ACT 270is brought toward Vcc in complementary fashion to the n-sense amplifier.With the low-voltage digitline approaching ground, there is a strongsignal to drive the appropriate p-channel transistor into conduction.

In an embodiment of the present invention, ROM cells are programmed toone logic state, but not the other. That is, all ROM cells can beprogrammed to logic zeros and not logic ones. The sense amplifiercircuitry is biased to sense the unprogrammed ROM cells as a logic onedata state. Thus, the sense amplifiers are biased to pull the activedigit line high in the absence of a programmed “zero” memory cell.

The present invention is not limited to the bias circuit describedabove, but can be any biasing technique which allows the sense amplifiercircuitry to favor one data state when the digit lines have a small, orzero, differential voltage. For example, the p-sense amplifier circuitcan be biased. Further, both the p-sense and n-sense amplifier circuitrycan be biased. In memory devices that use sense circuitry, which differsfrom the cross-couple circuit described, further biasing circuitry canbe used.

The present invention allows an embedded ROM to be fabricated in a DRAM,while programming the ROM cells using only one data state. Theabove-described embodiment biases the sense amplifier circuitry toaccurately read un-programmed memory cells. In other embodiments, digitline voltages are biased using reference memory cells to reliably senseun-programmed ROM cells, as described below.

Referring to FIG. 5, a portion of a ROM array is described. The arrayincludes a pair of digit lines 230 and 240 coupled to a differentialvoltage sense amplifier circuit 250. Each digit line can be selectivelycoupled to reference memory cells 260 and 262 to provide a differentialbetween the digit lines. In one embodiment, a reference cell 260 iscoupled to the active digit line 230 to bias the digit line toward theun-programmed state. In a complementary embodiment, reference cell 262is coupled to the reference digit line 240 to bias the reference digitline toward a programmed cell state. The reference cells can be ROMcells coupled to an intermediate voltage level X, such that ½ Vcc<X<Vcc,or Vss<X<½ Vcc. Alternatively, the reference cells can be DRAM capacitorcells that contain an appropriate charge that moves its correspondingdigit line voltage.

As illustrated in the timing diagram of FIG. 6, at time T1 the bit lines230 and 240 are equilibrated to ½ Vcc. At time T2, the memory cellwordline 220 is activated. At the same time, the reference wordline Ref₂is activated to couple the reference cell 262 to the reference digitline 240. If the ROM cell is un-programmed (not Vss), the active digitline 230 remains substantially at ½ Vcc and the reference digit linevoltage is decreased by un-charged reference cell 262. If the ROM cellis programmed to Vss, the active digit line 230 is pulled to Vss.

As illustrated in the timing diagram of FIG. 7, at time T1 the bit lines230 and 240 are equilibrated to ½ Vcc. At time T2, the memory cellwordline 220 is activated. At the same time, the reference wordline Ref₁is activated to couple the reference cell 260 to the active digit line230. If the ROM cell is un-programmed (not Vss) the active digit line230 is increased by charged reference cell 260, and the reference digit240 line voltage remains substantially at ½ Vcc. If the ROM cell isprogrammed to Vss, the active digit line 230 is pulled to Vss.

It will be appreciated by those skilled in the art, with the benefit ofthe present disclosure, that activating the ROM cell and the referencecell simultaneously can result in increased power consumption. As such,it may be beneficial to precharge the digit lines to a differentialstate prior to activating the ROM wordline. In this embodiment, thedifferential voltage remains present if the ROM cell is unprogrammed. Ifthe ROM cell is programmed, the differential voltage is driven hard inthe opposite direction.

In operation of this embodiment, the bias circuit is activated prior toactivating the ROM cell wordline. The reference digit line ispre-charged to a mid-level such as ½ Vcc and the active digit line ischarged to less than or equal to Vcc, but greater than ½ Vcc, prior toactivating the wordline. If the cell is programmed, the active digitline is discharge to ground.

The above biasing techniques allow for accurate sensing of un-programmedROM cells. Alternatively, the un-programmed memory cells can bepre-programmed and refreshed in a manner similar to standard DRAM.Referring to FIG. 8, a timing diagram of a single state ROM embeddedDRAM is described. In this example, the ROM cell is programmed to Vssusing the present substrate cell leakage and un-programmed ROM cells arecharged to Vcc. At time T1, the ROM memory cells are coupled to Vcc topre-charge the cells. The programmed ROM cells are also coupled to Vcc,but return to Vss following pre-charge. The discharge time depends uponthe leakage current of the hard programmed ROM cells. As stated above,the ROM cells should not be read until the cells discharge below Vcc.Over a period of time, the un-programmed ROM cell loses the pre-chargeand drops in charge. At time T2, the un-programmed ROM cells require arefresh. The refresh operation is substantially the same as thepre-charge operation. Controlling the ROM voltage during pre-program andrefresh operations can avoid contention between the programmed ROM cellsand the pre-charge voltage.

CONCLUSION

A ROM embedded DRAM has been described that provides ROM cells that canbe programmed to a single state. The ROM cells include capacitors havinga storage node. The storage node is processed to have a substantiallyhigh substrate leakage. The ROM cells, therefore, are hard programmed toa logic zero state. Bias techniques can be used to read un-programmedROM cells accurately. As described, sense amplifier circuitry can beoffset in one embodiment to default to the un-programmed state. Inanother embodiment, bias circuitry is coupled to bit lines to favor theun-programmed state. A differential pre-charge operation can also beused in another embodiment.

Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat any arrangement, which is calculated to achieve the same purpose,may be substituted for the specific embodiment shown. This applicationis intended to cover any adaptations or variations of the presentinvention. Therefore, it is manifestly intended that this invention belimited only by the claims and the equivalents thereof.

1. A method of fabricating a read only memory (ROM) cell comprising:forming a doped active area in an integrated circuit substrate; counterdoping the active area to increase conductivity between the active areaand the substrate; and forming a cell capacitor having a storage plateelectrically coupled to the active area.
 2. The method of claim 1,wherein the substrate is formed of a P-type material and the ROM cellactive areas are doped as N+ regions and counter doped with a P-typematerial.
 3. The method of claim 1, and further comprising: coupling acharge to the storage plate to pre-charge the ROM cell; and dischargingthe storage plate through the active area leakage current.
 4. The methodof claim 1, wherein the cell capacitor is formed as a stacked containercapacitor.
 5. The method of claim 1, and further comprising: forming asecond active area in the substrate and separated from the first activearea to define a channel region; and doping the second active area toenhance leakage current from second active area.
 6. A method of forminga read only memory (ROM) embedded dynamic random access memory (DRAM),comprising: forming an array of dynamic memory cells, each dynamicmemory cell comprising a storage capacitor having a storage platecoupled to first active area regions of a substrate, wherein the firstactive areas are doped to reduce a leakage current from the first activearea to the substrate; and forming an array of read only memory (ROM)cells, each ROM cell comprising a storage capacitor having a storageplate coupled to second active area regions of a substrate, wherein thesecond active areas are doped to enhance a leakage current from thesecond active area to the substrate.
 7. The method of claim 6, andfurther comprising coupling the storage plate of the ROM cell to thesecond active area of the substrate.
 8. The method of claim 7, andfurther comprising counter doping the second active area duringfabrication to increase conductivity between the second active area andthe substrate.
 9. The method of claim 6, wherein the substrate is formedof a P-type material and the second active areas are doped as N+ regionsand counter doped with a P-type material.
 10. The method of claim 6,wherein fabricating the storage capacitor of the dynamic memory cellsand the storage capacitor of the ROM cells are accomplished using astacked container capacitor process.
 11. The method of claim 6, whereinforming each ROM cell of the array of ROM cells comprises: forming thesecond active area in the substrate; doping the second active area toenhance a leakage current from the second active area to the substrate;and forming a cell capacitor having a ROM cell storage plateelectrically coupled to the second active area.
 12. The method of claim11, and wherein forming each ROM cell further comprises: coupling acharge to the ROM cell storage plate to pre-charge the ROM cell; anddischarging the ROM cell storage plate through the second active arealeakage current.
 13. The method of claim 11, wherein the substrate is ap-type material and the active area is an n-type material, whereindoping the active area to enhance a leakage current comprises counterdoping the active area with a p-type material.
 14. The method of claim13, wherein counter doping the second active area is performed usingboron.
 15. The method of claim 11, wherein the cell capacitor is formedas a stacked container capacitor.
 16. The method of claim 6, whereinforming each ROM cell of the array of ROM cells comprises: implanting N+material into a P-substrate to form the second active area; implanting aP-type material into the second active area to enhance a leakage currentfrom the second active area to the substrate; and forming a cellcapacitor having a storage plate electrically coupled to the secondactive area.
 17. The method of claim 16, wherein the P-type material isboron.
 18. The method of claim 16, wherein the cell capacitor is formedas a stacked container capacitor.